중복 비트로 오류를 수정할 수 있는 재구성 가능한 Non-Binary SAR/Single-Slope ADC

초록

This paper proposes reconfigurable hybrid analog to digital converter (ADC). The proposed hybrid ADC is combination with Successive Approximation Resister (SAR) ADC and Single-Slope (SS) ADC. Since SAR ADC used nonbinary CDAC, it consumes less power. SAR ADC has 1-bit redundancy bit, so it can correct error bit. This architecture is presented for wearable device application.