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초록
A 3.3V PLL is designed for a high frequency, low voltage, low power application. The designed circuit is simulated in a standard 0.6um CMOS technology. The designed voltage controlled oscillator(VCO) has a operating frequency of 80MHz-1GHz with good linearity. To improve voltage to frequency linearity, a new architecture is suggested. Also, PFD circuit is designed. PFD circuit's input operating frequency is 200MHz.
- 제목
- 넓은 록킹범위를 갖는 3.3V 고속 CMOS PLL 주파수 합성기
- 제목 (타언어)
- A 3.3V High Speed CMOS PLL Frequency Synthesizer with a Wide Locking Range
- 저자
- YOON KWANG SUB
- 학회명
- 제 5회 한국반도체학술대회