더블 부스트랩을 이용한 80MHz 샘플 앤 홀드

YOON KWANG SUB

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더블 부스트랩을 이용한 80MHz 샘플 앤 홀드

A 80 MS/s CMOS Sample and Hold circuit with double bootstrap circuit

YOON KWANG SUB

초록

In this paper, a fully differential high speed, high resolution CMOS sample and hold(S/H) circuit is designed for application of the Nyquist sampling ADC. The double bootstrap circuit is proposed to improve the linearity of S/H. The simulation result shows a conversion rate of 80MHz, SFDR (Spurious-free dynamic range) of 85dB, ENOB (Effective Number of Bits) of 13.8 bits and a power dissipation of 40mW at single voltage of 3.3V.

제목: 더블 부스트랩을 이용한 80MHz 샘플 앤 홀드

제목 (타언어): A 80 MS/s CMOS Sample and Hold circuit with double bootstrap circuit

저자: YOON KWANG SUB

학회명: 한국반도체학술대회