Design of Quaternary Logic gate Using Double Pass-transistor Logic with neuron MOS Down Literal Circuit

YOON KWANG SUB

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Design of Quaternary Logic gate Using Double Pass-transistor Logic with neuron MOS Down Literal Circuit

YOON KWANG SUB

초록

A multi-valued logic(MVL) pass gate is an important element to configure multi-valued logic. Multiple logical levels which are different from binary pass gates are required to be discriminated in MVL pass gates[1]. In this paper, we designed the Quaternary MIN(QMIN)/negated MIN(QNMIN) gate, the Quaternary MAX(QMAX)/negated MAX(QNMAX) gate using double pass-transistor logic(DPL) with neuron MOS threshold gate.

제목: Design of Quaternary Logic gate Using Double Pass-transistor Logic with neuron MOS Down Literal Circuit

제목 (타언어): Design of Quaternary Logic gate Using Double Pass-transistor Logic with neuron MOS Down Literal Circuit

저자: YOON KWANG SUB

학회명: The Thirty-Fourth International Symposium On Multiple-Valued Logic(ISMVL)