A CMOS Low Power 4th-Order Delta-Sigma Modulator with One Reconfigurable Amplifier

  • YOON KWANG SUB

초록

This paper describes the 4th-order feedback delta-sigma modulator with only one reconfigurable amplifier. The modulator is designed with 180nm CMOS standard process. The measurement results demonstrate the power dissipation of 352uW, peak SNDR of 82.41dB and the ENOB of 13.4bits with an input signal frequency of 250Hz, a sampling frequency of 128 kHz, an input signal bandwidth of 1kHz, and an oversampling rate of 64.

제목
A CMOS Low Power 4th-Order Delta-Sigma Modulator with One Reconfigurable Amplifier
저자
YOON KWANG SUB
학회명
Great Lake Sympoium on VLSI 2018
개최지
미국 시카고
학회 개최일
2018-05-23 ~ 2018-05-25