A 7bit 1GS/s High Speed CMOS A/D Converter for UWB Wireless Transceiver

초록

The UWB system requires a high-speed data transmission and low power consumption within a limited distance. In order to achieve the specification, it should employ a flash A/D converter architecture. But a flash architecture suffers from a poor dynamic performance, a large power dissipation, and a large chip area due to a large number of comparators. In order to enhance a dynamic performance of conventional flash A/D converter, this paper proposes a two stage latched comparator with a low voltage offset and a low power dissipation.