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Wafer-level, Patterned SWNT Device Array Based on Concentric Electrode Scheme
초록
Owing to their high surface-to-volume ratio and hollow cylindrical structure with every atom on the surface, the electrical characteristics of single-walled carbon nanotubes (SWNTs) are affected strongly by tiny surface perturbations. This ability makes it a promising candidate for many types of sensing applications. However, the process to build up a CNT sensor array still remains to be improved with respect to manufacturability. In this work, we propose a scalable fabrication process to achieve reliable and wafer-level patterning of SWNT network between electrodes. A SWNT network is formed on the fabricated test chip, in which concentric electrodes are embedded, using a dip-coating process. The concentric electrode has an inner electrode (Island Electrode, IE) enclosed by an outer electrode (Enclosing Electrode, EE) in which the SWNT network channel is confined to the area between the two electrodes. The concentric electrode itself provides a self-aligned SWCNT network channel. This self-alignment scheme is simple and quite useful because the SWCNTs can be coated on the entire test chip without the need for cumbersome processes. As a result, the present fabrication meets the following requirements: (1) mask-free process, (2) low temperature process, (3) the uniformity and the reproducibility of CNT sensor, and (4) the scalability and the compatibility with the well-established micromachining process.
- 제목
- Wafer-level, Patterned SWNT Device Array Based on Concentric Electrode Scheme
- 저자
- TAE JUNE KANG
- 학회명
- The 14th International Symposium on Microelectronics and Packaging
- 개최지
- KINTEX, Ilsan/Seoul, Korea
- 학회 개최일
- 2015-10-13 ~ 2015-10-15