Process and Device Simulation Based on Atomistic and Quantum Mechanical Approach in the Regime of sub-50nm Gate Length

Process and Device Simulation Based on Atomistic and Quantum Mechanical Approach in the Regime of sub-50nm Gate Length
  • WON TAEYOUNG

초록

In this paper, we report simulation methods based on atomistic approach for sub-50nm gate length. Molecular dynamics (MD) is implemented for the ion implantation process to form ultra-shallow junctions [5-6]. And then, the diffusion process is simulated by using kinetic Monte Carlo (KMC) with the damages and dopants distribution from ion implantation in MD [7]. A device simulation is performed by using profiles from the results of KMC. As an exemplary case, we demonstrate FinFET of 20nm physical gate length.

제목
Process and Device Simulation Based on Atomistic and Quantum Mechanical Approach in the Regime of sub-50nm Gate Length
제목 (타언어)
Process and Device Simulation Based on Atomistic and Quantum Mechanical Approach in the Regime of sub-50nm Gate Length
저자
WON TAEYOUNG
학회명
2003 International Microprocesses and Nanotechnology Conference