A Study on the Design of Flash Analog to Quaternary Converter Using DLC Comparator

초록

This paper describes a 3.3V low power 4 digit CMOS flash analog to quaternary converter (AQC) designed with neuron MOS down literal circuit comparators and binary to quaternary encoding blocks. The neuron MOS down literal comparator allows the designed AQC to reduce not only the number of MOS transistors, but also power dissipations compared with conventional ADCs. Fast settling time and low power consumption of the AQC are achieved by utilizing the proposed architecture. The simulation results of the designed 4 digit AQC show a sampling rate of 6MHz and a power dissipation of 1mW with a single power supply of 3.3V for a double poly four metal standard CMOS 0.35㎛ n-well technology.