저전력 10비트 플래시-SAR CMOS ADC 설계

초록

This paper proposed a low power CMOS Flash-SAR ADC which consists of a Flash ADC for 2 most significant bits and a SAR ADC with capacitor DAC for 8 least significant bits. Employment of a Flash ADC allows the proposed circuit to enhance the conversion speed. The SAR ADC with capacitor DAC provides a low power dissipation. The proposed ADC consumes 136 with a power supply of 1V under a 0.18 CMOS process and achieves 9.16 effective number of bits for sampling frequency up to 2MHz. Therefore it results in 120fJ/step of Figure of Merit (FoM).