FPGA-based implementation of synchronous Petri Nets

초록

This paper describes a flexible and systematic implementation method of Petri-Nets that can be applied to high speed parallel control. This paper suggests a hird-wired implementation for high frequency clock-driven system with little jitter. To implement Petri Nets with synchronous (clock-driven) digital circuits, Synchronous Petri Net is proposed. The suggested implementation method is based on a regular cell-array such as FPGA(field programmable gate array).