A 3.3V high Speed CMOS PLL with Wide Input Locking Range

초록

A 3.3V PLL(Phase Locked Loop) is designed for a high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage-to-frequency linearity of VCO(Voltage Controlled Oscillator). The designed VCO operates at a wide frequency range of 75.8MHz-1GHz with a good linearity. PFD(Phase Frequency Detector) circuit preventing fluctuation of the charge pump circuit under the locked condition is designed. The simulation results of the PLL with a standard 0.6um CMOS technology illustrate a locking time of 3.5us, +/-100ps jitter and a power dissipation of 92mW at 1GHz operating frequency with 125MHz of input frequency.