A High-Speed HBM Receiver Design for High-Performance Computing Systems

초록

In this paper, we present a receiver design that achieves high data rates while maintaining low power consumption for high bandwidth memory (HBM) applications, using 28-nm CMOS technology. The proposed receiver scheme incorporates an analog front-end with an active inductor and wide-range peaking control, effectively compensating for the significant losses from heavy capacitive loading in a multi-stack through-silicon-via (TSV) I/O channel at a low supply voltage of 0.7 V. Simulation results indicate that the receiver can process data at a rate of 11 Gb/s, consuming 1.15 mW of power in a 1 pF, 12-stacked HBM configuration. Additionally, the proposed receiver achieves an energy efficiency of 0.104 pJ/b/pF, demonstrating its potential for enhancing HBM system performance. © 2024 IEEE.

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