Design of 10-bit SAR ADC with Enhancement of Linearity on C-DAC Array

초록

The block diagram of the proposed 10-bit SAR ADC is shown in Fig. 1. The proposed SAR ADC consists of differential 10-bit C-DAC arrays top and bottom, a power on reset circuit with clock, a dynamic latched compactor, one S/R flip-flop, 10-bit SAR logic, and output register.The circuit schematic of the proposed top and bottom 10-bit capacitor DAC arrays within the proposed SAR ADC, includes one split capacitor, four equivalent MSB capacitors with switches, and binary-weighted capacitors. The analog input signal charges the sampling capacitors of the MSB node in the first place. Therefore MSB capacitor is one of the most crucial one to influence linearity of C-DAC. Dividing MSB node into 4 parts has an effect on enhancing linearity.