A 8-bit 2MS/s SAR ADC with Pre-Amplifier in 350-nm CMOS

A 8-bit 2MS/s SAR ADC with Pre-Amplifier in 350-nm CMOS
  • YOON KWANG SUB

초록

This paper proposes a 8-bit SAR ADC with Pre-Amplifier. which is appropriate for human interface with a device such as a touch pad. Recently, high performance and high operation speed of devices require low power and small chip size. For the above reasons, operation at a high sampling frequency is required. The SAR A/D Converter have a high speed comparator with CLK. This high speed CLK affects the voltage of the C-DAC through the comparator. This is a kickback noise. Preamplifier can be placed between the comparator and C-DAC to prevent this noise. The result of the comparator are more accurate and better A/D converter performance can be obtained.

제목
A 8-bit 2MS/s SAR ADC with Pre-Amplifier in 350-nm CMOS
제목 (타언어)
A 8-bit 2MS/s SAR ADC with Pre-Amplifier in 350-nm CMOS
저자
YOON KWANG SUB
학회명
정보 및 제어 학술대회 CICS 2017
개최지
목포
학회 개최일
2017-10-26 ~ 2017-10-28