Behavioural Modelling and Verification of a Novel Weighted System-Level Chopping for High-Resolution Incremental ADCs

초록

The system-level chopping (SLC) technique attenuates low-frequency noise, such as 1/f noise, particularly in an incremental analogue-to-digital converter (IADC). To achieve additional low-frequency noise attenuation, SLC can be utilised together with dynamic offset cancellation (DOC) techniques such as correlated double sampling (CDS) and auto-zeroing (AZ). In this letter, a novel weighted system-level chopping (WSLC) technique is proposed to achieve a further suppressed low-frequency noise characteristic. By applying the proposed WSLC with a dynamic circuit weight, a third-order high-pass noise transfer function (NTF) can be achieved efficiently. Consequently, with the noise weight of 0.9, it provides a 1/f noise suppression of 78.94% compared to the conventional second-order SLC technique while maintaining the same ADC latency.

키워드