The system performance analysis of out-of-order superscalar processors using analytical method

초록

This paper presends an analytic model to predict the instruction execution rate of out-of-order issue superscalar processors. Most of previous works have simply employed simulation methods to predict the performance of superscalar processor or to measure the effects of instruction level parallelism and cache miss. However, simulation-based methods cannot uncover the exact causes of performance bottleneck. This paper suggests an analytical method to predict instruction execution rates using a queueing midel with finete-buffer size and synchronous operation mode. The proposed model takes into account various architectural parameters such as snstruction level parallelism, branch probability, branch prediction accuracy, reorder buffer size, and cache miss. It can also analyze the performance relationship between cache and pipeline. To prove the correctness of the model, we performed simulations with several instruction traces. The simulation results showed that the proposed model can estimate the average execution rate within 10% error for most benchmark programs. The model is also able to provide a valuable information about the effect of the cache miss on the performance of out-of-order issue superscalar processors