An energy-efficient multi-level RF-interconnect for global network-on-chip communication

초록

A simultaneous and reconfigurable multi-level RF-interconnect (MRI) for global network-on-chip (NoC) communication is demonstrated. The proposed MRI interface consists of baseband (BB) and RF band transceivers. The BB transceiver uses multi-level signaling (MLS) to enhance communication bandwidth. The RF-band transceiver utilizes amplitude-shift keying (ASK) modulation to support simultaneous communication on a shared single-ended on-chip global interconnect. A phase-locked loop (PLL) using a sub-harmonic multiply-by-10 injection-locked frequency multiplier is also designed to support a fully-synchronous NoC architecture. A differential voltage-controlled oscillator (VCO) used in a PLL creates an output frequency for a frequency range between 0.5 and 2.65 GHz signal. The multiply-by-10 ILFM generates 10 times higher frequency than the VCO output signal. Using the proposed multiply-by-10 ILFM can minimize the number of power-hungry frequency divider stages in a PLL feedback loop, resulting in improvement of the MRI power efficiency. The MLS-based BB and ASK-based RF band carry 10 Gb/s/pin and 4.4 Gb/s/pin, respectively. The proposed system is fabricated in a 65 nm CMOS process and achieves an energy efficiency of 2 pJ/b.

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