PCS용 2.5V Si CMOS 저잡음 증폭기 설계

초록

In this paper, a 1.8GHz low noise amplifier was designed and simulated using 0.25㎛ Si CMOS process. Noise characteristics and s parameters were extracted for the 300㎛ gate width and 0.25㎛ gate length NMOS transistors. For high available power gain, each stage was designed cascode type. It revealed available power gain of 23.5㏈, noise figure of 2.0㏈, power consumption of 15㎽ at 2.5V. It was shown that designed low noise amplifier had good RF performance. Designed Si CMOS LNA is expected to be used for RF front-end in transceiver.