A CMOS PFM buck converter employing a digitally programmable voltage level-shifting technique

초록

This paper describes a CMOS pulse frequency modulation (PFM) buck converter employing a digitally programmable voltage level-shifting technique capable of adjusting peak inductor current and output ripple voltage for different load currents. The conventional PFM buck converters employ either an adaptive delay time control circuit or a fixed delay time control circuit to control output ripple voltage and power efficiency with the switching frequency. However, they suffer from a large peak inductor current, resulting in reduced power efficiency. The digitally programmable voltage level-shifting circuit, based on a common source amplifier, is capable of sensing inductor current through the voltage drop caused by on-resistance of the power switch, and can control peak inductor current. The precision needed to control the magnitude of the peak inductor current can be obtained with the number of bits in the digitally programmable voltage level-shifting circuit that are dependent on the input common mode range of the comparator. Employment of one comparator with pre-control logic and post-control logic circuits allows the proposed circuit to improve power efficiency by removing additional circuits, compared with the conventional PFM buck converters. The proposed converter was implemented with a 180nm CMOS process. The effective chip size of the core block occupies 900mx590m. The proposed PFM mode buck converter with a precision of four bits to control peak inductor current is capable of accommodating an input voltage range of 2.7-3.3V, and can produce output voltage of 1.2V. The operational switching frequency measured is on the order of several to several hundred kHz, the load current range is under 150mA, and the measured output ripple voltage varied, depending on the digital programming status. The measured power efficiency ranged between 70 and 84%.

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