뉴런 모스 DLC를 이용한 동기식 4치 up/down 카운터 설계

초록

In this paper, quaternary logic gates using Down literal circuit(DLC) has been designed, and then synchronous quaternary up/down counter using those gates has been proposed. The proposed counter consists of T-type quaternary flip flop consists of D-type quaternary flip flop and quaternary logic gates(module-4 addition gates, quaternary inverter, identity cell, 1-of-4 MUX). The simulation result of this counter show delay time of 14[ns] and power consumption of 2.35[mW]. Also, assigning the designed counter to MVL(Multiple-valued Logic) curcuit, it has advantages of the reduced interconnection and chip area as well as easy expension of digit.