A Pipeline Schedule and Data Reuse Scheme for Merge Mode Operations in a Hardware-based HEVC Encoder

초록

The merge mode is a new compression tool in High Efficiency Video Coding (HEVC) proposed to reduce a bitrate significantly by sharing motion information between neighboring blocks. However, for hardware implementation, the merge mode causes a significant bottleneck in encoding operations. For fast processing of the merge mode, parallelism should be exploited in terms of computation and memory access. This paper proposes a pipeline schedule and a data-reuse scheme to speed up merge mode operations given the limited memory bandwidth. Experimental results show that the proposed merge mode design with 210 K logic gates processes 32x32 coding tree units within 980 cycles at the operating frequency of 150 MHz.