A Study on the Highly Parallel Multiple-Valued Logic Circuit design Method based on the DTG

초록

This paper proposes algorithms that design the highly parallel multiple-valued logic circuit of DTG (Directed Tree Graph) to be represented by tree structure relationship between input and output of nodes. The conventional Nakajima's algorithms have some problems so that this paper introduce the concept of mathematical analysis based on tree structure to design optimized locally computable circuit. Using the proposed circuit design algorithms in this paper, it is possible to design circuit in that DTG have any node number - not able to design by Nakajima's algorithms. Also, making a comparison between the circuit design using Nakajima's algorithms and this paper's, we testify that proposed algorithms in this paper optimize circuit design all case of DTG. Some examples are shown to demonstrate the usefulness of the circuit design algorithm.