TARO: Automatic Optimization for Free-Running Kernels in FPGA High-Level Synthesis

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초록

Streaming applications have become one of the key application domains for high-level synthesis (HLS) tools. For a streaming application, there is a potential to simplify the control logic by regulating each task with a stream of input and output data. This is called free-running optimization. But it is difficult to understand when such optimization can be applied without changing the functionality of the original design. Moreover, it takes a large effort to manually apply the optimization across legacy codes. In this article, we present the TARO framework which automatically applies the free-running optimization on HLS-based streaming applications. TARO simplifies the control logic without degrading the clock frequency or the performance. Experiments on Alveo U250 shows that we can obtain an average of 16% LUT and 45% FF reduction for streaming-based systolic array designs.

키워드

Index Terms-Field programmable gate arrays (FPGA)free running optimizationhigh level synthesis (HLS)
제목
TARO: Automatic Optimization for Free-Running Kernels in FPGA High-Level Synthesis
저자
Choi, Young-KyuChi, YuzeLau, JasonCong, Jason
DOI
10.1109/TCAD.2022.3216544
발행일
2023-07
유형
Article
저널명
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
42
7
페이지
2423 ~ 2427