Topography Simulation for Wafer-scale Structural Analysis

초록

Many research efforts have been made on the development of novel schemes which allows the designer to figure out the topographical evolution of the surface during the front-end semiconductor process such as deposition and etching. Exact understanding of topographical evolution is important for optimizing the front-end process in nanometer semiconductor process. There have been proposed many excellent schemes like string method and level-set method for the computer simulation of topography. The conventional string method, however, causes fatal errors such as the looping of strings from time to time, while the level set method seems to be computationally inefficient for tracking the evolution of interfaces. Furthermore, the cell method has a unique feature such as the capability to easily handle the topographical evolution, adaptive meshing scheme, and relatively simplicity for the extension to the three-dimension. However, the traditional cell method has a limit because it requires intensive memory. In this paper, we propose a cell advancing method which demonstrates the improvement in comparison with the traditional cell method for accurate topography simulation. For the subsequent FEM procedure, mesh generation is conducted in the simulated volume of topography. The proposed method simulates the advancement and backward movement of the surface through a list structure, so called the surface cell list. And intensive memory requirement is reduced by dynamically allocating topography information only at surface cells. The surface cells are constituted the list for the efficiency of the memory and computation. The simulation region is divided up into hexahedron-shaped cells. The resulting divided cells are separated into three kinds. The separated cells of three kinds employ surface cell, reference cell and substrate.