Step-Efficient Parallel Implementation of n-bit Full Adders Using Stateful Logic in Memristor Crossbar Arrays

초록

Memristor-based stateful logic offers a promising solution for in-memory computing by mitigating the von Neumann bottleneck and minimizing data movement between memory and processing units. At the heart of this approach, primitive logic circuits, primarily constructed from resistive switching memory (memristor) units, serve as the foundational elements of stateful logic families. However, the stochastic switching behavior of memristors can compromise computational accuracy, necessitating optimization strategies to ensure reliable and robust logic operations. In this work, we investigate the switching voltage distributions of memristors with an Al2O3/TiOx/TiOy structure and utilize their multilevel state tunability to propose a novel stateful logic architecture along with an optimization method to enhance operational reliability across various logic types. The proposed optimization strategy is experimentally validated, demonstrating high logic fidelity under all input conditions. Furthermore, a 1-bit full adder, a fundamental arithmetic logic unit, is implemented by cascading the developed stateful logic gates. Finally, this study presents a parallel operation method for stateful logic in a crossbar array, enabling n-bit full adder implementation with a reduced number of computational steps by maximizing parallelism.

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