Design of 1.5V-3GHz CMOS multi loops chained two stages VCO

초록

This paper proposes a multi-chained two stages CMOS VCO circuit based on a differential ring oscillator to improve a phase noise performance. The proposed multi-chained architecture is able to reduce a timing jitter or a transition spacing. The ring oscillator with a short jitter variation is expected to exhibit a low phase noise. The newly designed differential delay cell is expected to operate in high frequency.