A Dual band CMOS VCO with a balanced duty cycle buffer

초록

This paper proposes a dual band VCO with a standard 0.35㎛ CMOS process to generate 1.07GHz and 2.06GHz. The proposed VCO architecture with 50% duty cycle circuit and a half adder(HA) is able to produce a frequency two times higher than that of the conventional VCOs. The measurement results demonstrate that the gain of VCO and power dissipation are 561MHz/V and 14.6mW, respectively. The phase noises of the dual band VCO are measured to be -99.05dBc/Hz and -94.9dBc/Hz at 2MHz offset from 1.07GHz and 2.06GHz.