The Design of Ternary D flip-flop Using Ternary Logic Gate

초록

In this paper, we designed ternary logic gate that has neuron MOS(vMOS) pass transistor on voltage mode and ternary D flip-flop. The ternary logic gates were designed with transmission function using DLC (Down Literal Circuit) that has various threshold voltages. In this paper, these circuits used 3.3V supply voltage and 0.35um process parameter, and also represented HSPICE simulation result.