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High-speed low-complexity Reed-Solomon decoder using pipelined Berlekamp-Massey algorithm
초록
This paper presents a high-speed low-complexity pipelined Reed-Solomon (RS) decoder using pipelined reformulated inversionless Berlekamp-Massey (pRiBM) algorithm. Also, this paper offers technique which is about efficient method of pipelining at the RS decoders. This architecture uses pipelined Galois-Field (GF) multipliers in Syndrome computation block, key equation solver (KES) block, Forney and Chien search blocks so as to enhance clock frequency. A high-speed pipelined RS decoder based on the pRiBM algorithm has been designed and implemented with IBM 90-nm CMOS standard cell technology in a supply voltage of 1.2 V. The proposed RS decoder operates at a clock frequency of 690 MHz and has a throughput of 5.52 Gb/s. The proposed architecture requires approximately 18% fewer gate counts than architecture based on the pipelined degree- computationless modified Euclidean (pDCME) algorithm [5]. ©2009 IEEE.
- 제목
- High-speed low-complexity Reed-Solomon decoder using pipelined Berlekamp-Massey algorithm
- 저자
- HANHO LEE
- 학회명
- International SoC Design Conference
- 학회 개최일
- 2009-11-23 ~ 2009-11-24