3D Modeling of Stacked Structure on Semiconductor Substrate

초록

This paper reports a numerical method for extracting parasitic parameters and its application to a complex geometry on a semiconductor wafer. In order to produce a complex three-dimensional structure from the mask layout data, a topography simulation is undertaken in accordance with the given process recipe comprising various depositions and deching process steps. A finite element method (FEM) has been employed for calculating a potential distribution and extracting device parameters present in a cell capacitor and intervening interlayer dielectric. A concave cylindrical DRAM cell capacitor with a minimum feature size of 0.25 ㎛ was chosen as a test vehicle to check the validity of the simulation. In this work, 62 parasitic capacitance with 4 cell capacitance were extracted from a stacked DRAM cell structure over a bit line.