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초록

This paper reports a methodology and its application for extracting cell capacitances and parasitic capacitances in a stacked DRAM cell structure by a numerical technique. To calculate the cell and parasitic capacitances in a stacked DRAM cell, we employed finite element method (FEM) and calculated the distribution of electric potential in the inter-metal layer dielectric (ILD) by solving Laplace's Equation. The estimated capacitances coincides with the measured data and can be employed to model the multiple level interconnection structure.