RLC Reduction Scheme for Modeling Interconnection Line Delay in Nano-CMOS Circuits

초록

In this paper we propose a realizable RLC-in-RLC-out technique to reduce parasitic parameters. The proposed technique is an efficient MOR (Model Order Reduction) method, which makes it possible to control the rise and delay time errors within the limit corresponding to the maximum frequency of operation. In addition, the equivalent circuit with reduced number of node elements derived from the proposed algorithm does conserve the passivity due to the use of zero-th or first order approximation. The proposed algorithm from node elimination is based on TICER (Time Constant Equilibration Reduction) approach. The reduction is achieved by eliminating the so-called quick nodes which have time constant less than the user-defined time constant. The nodal time constant is a maximum value between the RC time constant and LC time constant. For an exemplary circuit with 19,600 elements, the simulation revealed that we have maximum 0.6 % error rate at 97 % reduction rates.