A Fully Synthesizable 12-bit Event-Driven TDC-Assisted Two-Step Counter for Imagers Achieving 0.49-LSB INL in 28-nm CMOS

초록

This brief presents a fully synthesizable 12-bit event-driven time-to-digital converter (TDC)-assisted two-step counter for column-parallel single-slope analog-to-digital converters (SS-ADCs) in image sensors. The proposed two-step architecture employs a 10-bit hybrid coarse counter-comprising a 2-bit Gray counter and an 8-bit ripple counter-with a 2-bit event-driven TDC for fine counting. A dual-edge stop generator triggers the event-driven TDC only on a comparator output (CMP OUT ) transition, so the event-driven TDC is active for no longer than half a counter clock (CLK CNT ) period, effectively reducing dynamic power consumption. Since coarse and fine operations proceed in parallel, the required conversion time for 12-bit quantization is reduced to one quarter of that of a ripple-counter-only approach. With an active area of 62.04 mu m(2), the prototype was fabricated in a 28-nm CMOS process using only standard cells. The measured power consumption is 1.48 mu W, achieving 72.1% and 53.3% power reduction compared with the conventional 12-bit two-step and ripple-counter-based implementations, respectively. The event-driven TDC for residual time quantization consumes only 34 nW. The measured integral nonlinearity (INL) is +0.49/-0.47 LSB with an operating clock of 1.16 GHz, confirming relatively high linearity for imagers.

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