Process Development of Copper Metallic Coating on Polished Silicon Wafers via Electroplating for Semiconductor Applications

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Copper electroplating on semiconductor wafers is recognized as a critical process for realizing low-resistance and high-reliability metallic conductors in next-generation integrated circuits. In this work, a p-type semiconductor wafer was polished with sandpaper, and copper films were deposited using a plating solution developed by the research team, applying a half-wave rectified alternating current voltage. To examine the evolution of surface morphology and electrical properties, samples were prepared after deposition for 2, 5, 10, 20, 40, and 60 min. Microscopic analysis demonstrated that the 10 min sample retained polishing traces, whereas these marks disappeared in samples plated for longer than 20 min. At 40 and 60 min, the surface roughness became uniform in both vertical and horizontal directions. Scanning electron microscopy indicated that copper was not uniformly deposited until 20 min, while by 40 min the entire substrate was covered with a continuous copper layer. Cross-sectional observations showed that film thickness increased up to 10 min, achieved complete surface coverage by 40 min, and thickened further thereafter. X-ray diffraction analysis indicated that the (111) orientation was predominant and remained stable throughout the plating process.

키워드

CopperPolished silicon waferElectroplatingHalf-wave rectified alternating current voltageSurface morphology
제목
Process Development of Copper Metallic Coating on Polished Silicon Wafers via Electroplating for Semiconductor Applications
저자
민성기김경보김무진
DOI
10.5757/ASCT.2025.34.6.188
발행일
2025-11
유형
Article
저널명
한국진공학회지
34
6
페이지
188 ~ 193