ScholarWorks@인하대학교

상세 보기

6bit 1GSs Interpolation Flash ADC with two-stage latch comparator

6bit 1GSs Interpolation Flash ADC with two-stage latch comparator
  • YOON KWANG SUB
제목
6bit 1GSs Interpolation Flash ADC with two-stage latch comparator
제목 (타언어)
6bit 1GSs Interpolation Flash ADC with two-stage latch comparator
저자
YOON KWANG SUB
학회명
ITC-CSCC2007

ScholarWorks@인하대학교

22212 인천광역시 미추홀구 인하로 100 정석학술정보관 Tel. 032-860-9003

COPYRIGHT © 인하대학교 All Rights Reserved.

Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.

You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.