A survey on vertical interconnection and topology of three-dimensional network-on-chip

초록

The three-dimensional network-on-chip (3D NoC) has been proposed with the continuous advancement of integrated circuits (ICs) to address the inherent limitations of conventional two-dimensional NoC (2D NoC) architectures. 3D NoCs introduce direct vertical inter-layer electrical connections, enabling the integration of additional processing elements (PEs) within a limited area, hence significantly enhancing integration density and communication efficiency. However, the performance and scalability of 3D NoCs are highly dependent on vertical interconnection technologies and topology designs. In this survey, we discuss the development of 2D and 3D IC/NoC, providing a comprehensive overview of various vertical interconnection technologies evolved from conventional bonding to through-via (especially through-silicon-via) and to contactless connection. Additionally, we categorize the topologies of 3D NoCs based on their shapes and compare their degree, diameter, connections, and bisection bandwidth. The current challenges and future research opportunities are discussed to provide a foundation for the continued advancement and development in 3D NoCs.

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