Configurable Memory-Based NTT Architecture for Homomorphic Encryption

초록

Fully Homomorphic Encryption (FHE) is currently seen to be a promising solution for privacy-preserving applications. However, FHE suffers from a computational bottleneck due to the need to perform large polynomial calculations. Number Theoretic Transform (NTT) as a fundamental component of FHE is widely used to reduce latency and computation complexity while performing polynomial multiplication. Designing FHE can be challenging because it requires different settings depending on the application, such as the polynomial degree and coefficient modulus size. The hardware design has to stick to specific parameter values, which can make things harder to be implemented. In this work, we present a configurable hardware accelerator for NTT that supports a wide range of parameter settings without any recompilation. This module is highly parallelized and designed for high throughput on the butterfly unit array. We provide a conflict-free access memory between the NTT Core and memory to increase performance. For the evaluation, our NTT and INTT modules show significant performance improvements compared to the CPU implementation using Microsoft's SEAL 4.0 library by factors of 8.88x and 11.2x, respectively. In comparison with the state-of-the-art hardware implementation, our module showed better performance with 1.46x improvement of throughput/slice metric as a fair comparison while consuming fewer hardware resources.

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