A 3.3V High Speed CMOS PLL with 3-250 MHz Input Locking Range

초록

This paper describes a dual-looped PLL architecture to improve voltage-to-frequency linearity of VCO. The designed VCO operates at a wide frequency range of 75.8MHz-IGHz with a good linearity. PFD circuit preventing fluctuation of the charge pump circuit under the locked condition is designed Experimental results show that the phase noise of VCO with V-I converter is -100.3dBc/Hz at a I OOkHz offset frequency and the power dissipation is 92m W.