Silane-Assisted Surface Functionalization Method for Die Attach Film-Free Stacking Semiconductor Packaging Application

초록

Three-dimensional (3D) chip stacking is attracting significant attention due to the growing importance of heterogeneous integration in semiconductor packaging. However, developing new stacking approaches that ensure high thermal conductance and reduced package height without the use of die attach films (DAFs) remains a challenge. In this study, we present a silane-assisted surface functionalization method for DAF-free silicon chip stacking. Amine and epoxy groups from silane precursors were introduced onto silicon chip surfaces through a simple immersion treatment. The functionalized chips were then directly bonded, forming a high-thermal-conductance packaging structure. Thus, this silane-based functionalization offers a simple and effective route for next-generation 3D chip stacking in advanced heterogeneous integration. 본 연구는 2025년도 정부(교육부) 재원으로 한국연구재단의 지원을 받아 수행된 기초연구사업임(RS-2022-NR070869).? Keywords: Semiconductor packaging, Heterogeneous integration, Silane functionalization, Thermal conductance, Die attach film-free