A 6-bit 2-GS/s CMOS Flash A/D Converter

YOON KWANG SUB

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A 6-bit 2-GS/s CMOS Flash A/D Converter

YOON KWANG SUB

초록

This paper describes a 6-bit 2GS/s CMOS flash A/D converter for UWB applicaion. The proposed flash architecture employs comparators with a bistable circuit for low power dissipation and PLL for chip measurement.

제목: A 6-bit 2-GS/s CMOS Flash A/D Converter

제목 (타언어): A 6-bit 2-GS/s CMOS Flash A/D Converter

저자: YOON KWANG SUB

학회명: International SoC Design Conference