A Low-Complexity Bit-Parallel Multiplexer-Based Multiplier for a class of finite fields

초록

The two key points for computing multiplication over a class of fields GF(2m) are polynomial multiplication and modular reduction. Two methodologies are newly induced by the properties of the modified Booth's algorithm and irreducible all one polynomials, respectively. Then a low complexity multiplexer-based multiplier is presented based on the aforementioned methodology. Proposed our multiplier consists of m 2-input AND gates, an {m(m+3)/2-2} 2-input XOR gates, and m(m-1)/2 4X1 multiplexers. For the detailed estimation of the complexity of our multiplier, we will expand this argument into the transistor count, using a standard CMOS VLSI realization. The compared results show that our work is advantageous in terms of circuit complexity and requires less delay time compared to previously reported multipliers. Moreover, our architecture is very regular, modular and therefore, well-suited for VLSI implementation.