동적 부분 재구성 방식을 이용한 재구성형 Booth 곱셈기의 구현

초록

Reconfigurable hardware devices make it possible to change the topology of electronic circuits. This paper deals with a dynamic partial reconfiguration method to the design of reconfigurable Booth multiplier using Xilinx Virtex2 FPGAs. This method shows small configured slice, fast reconfiguration speed and good area efficiency as compared with conventional full reconfiguration method. The proposed method could open the way towards defining a business model for dynamic self-reconfiguration hardware or evolvable hardware.