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Extraction of Coupled PLC Network from Multi-level Imterconnects for Full Chip Simulation

Extraction of Coupled PLC Network from Multi-level Imterconnects for Full Chip Simulation
  • WON TAEYOUNG
제목
Extraction of Coupled PLC Network from Multi-level Imterconnects for Full Chip Simulation
제목 (타언어)
Extraction of Coupled PLC Network from Multi-level Imterconnects for Full Chip Simulation
저자
WON TAEYOUNG
학회명
Technical Preceedings of the forth International Conference on Modeling and Simulation of Microsystems(MSM'2002)

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