Design of an Inverter-based 3rd Order ΔΣ CMOS Modulator using a 1.5 bit Comparator and Analog Adder

초록

This paper describes an inverter-based third order Delta Sigma CMOS modulator with a 1.5 bit comparator and analog adder circuit for audio signal processing on IoT. In order to minimize the power consumption of the proposed modulator, the inverters embedded into integrators and an analog adder are to operate in weak inversion region with analog and digital power supply of 0.8 V and 1.8 V, respectively. The proposed modulator is implemented in an 180 nm standard CMOS process. The core layout area of the delta-sigma modulator occupies 0.36 mm(2). The measurement results demonstrate peak SNDR of 80.7 dB, ENOB of 13.1 bit, DR of 86.1 dB, analog power dissipation of 28.8 uW, digital power dissipation of 66.6 uW, total power dissipation of 95.4 uW, FOM(walden) of 269 fJ/step, and FOM(schreier) 169.3 dB at sampling frequency of 2.56 MHz and input signal frequency of 2.5 kHz.

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