Design of Quaternary Logic gate using Double Pass-transistor Logic with neuron MOS Threshold gate

초록

A multi-valued logic(MVL) pass gate is an important element to configure multi-valued logic. different from binary pass gates, multiple logical levels are required to bediscriminated in MVL pass gates. In this paper, We designed the Quaternary MIN(QMIN)/negated MIN(QNMIN) gate, the quaternary MAX(QMAX)/negated MAX(QNMAX) gate using double pass-transistor logic(DPL) with neuron MOS(vMOS) threshold gate. DPL is improved the gate speed without increasing the input capacitance. It has a symmetrical arrangement and double-transmission characteristics. The threshold gates composed by vMOS down literal circuit(DLC). The proposed gates get the valued to realize various multi threshold voltages. In this paper, these circuits are used 3V power supply coltage and parameter of 0.35um N-well 2-poly 4-metal CMOS technology, and also represented HSPICE simulation results.