A CMOS 6 bit 250MS/s A/D Converter with input voltage range detectors

YOON KWANG SUB

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A CMOS 6 bit 250MS/s A/D Converter with input voltage range detectors

YOON KWANG SUB

초록

This paper proposes a CMOS 6 bit A/D converter with input voltage range detectors based upon folding amplifier with a folded-cascode load. The input voltage range detectors allow the proposed A/D converter to reduce the power dissipation by turning on one fourth of all the comparators. The measurement result illustrates ENOB of 5.1 bits at 250Msps, power dissipation of 106mW, and FoM of 17.5pJ/steps.

제목: A CMOS 6 bit 250MS/s A/D Converter with input voltage range detectors

저자: YOON KWANG SUB

학회명: IEEE International SoC Conference (SOCC)

개최지: Nevada 주 Bally's Las Vegas 호텔

학회 개최일: 2010-09-27 ~ 2010-09-29