디지털신경회로망의 하드웨어구현을 위한 재구성형 모듈러 디자인의 적용

초록

In this paper, I propose a new architecture for hardware implementation of digital neural network, called ERNA(Expandable and Reconfigurable Neural network Architecture). By adopting flexible ladder-style bus and internal connection network into the digital neural network based on traditional SIMD architecture, the proposed architecture enables fast processing that is based on parallelism and pipelining, while does not abandon the flexibility and expandibility of the traditional approach. In the proposed architecture, users can change the network topology by setting configuration registers. Such reconfigurability on hardware allows enough usability like software simulation. I implement the proposed design on real FPGA, and configure the chip to multi-layer perceptron with back propagation learning for alphabet recognition problem. Performance comparison with its software counterpart shows its value in the aspects of performance and flexibility.