균형잡힌 듀티싸이클 버퍼를 가진 3.3V 이중대역 CMOS 전압제어발진기

A 3.3V Dual band CMOS VCO with a Balanced Duty Cycle Buffer
  • YOON KWANG SUB

초록

This paper proposes a dual band VCO with a standard 0.35㎛ CMOS process to generate 1GHz and 2GHz. The proposed VCO architecture with 50% duty cycle circuit and a half adder(HA) is able to produce a frequency two times higher than that of the conventional VCOs. The measurement results demonstrate that the gain of VCO and power dissipation are 561MHz/V and 14.6mW, respectively. The phase noises of the dual band VCO are measured to be -82.7dBc/Hz and -79.2dBc/Hz at 2MHz offset from 1.07GHz and 2.1GHz.

제목
균형잡힌 듀티싸이클 버퍼를 가진 3.3V 이중대역 CMOS 전압제어발진기
제목 (타언어)
A 3.3V Dual band CMOS VCO with a Balanced Duty Cycle Buffer
저자
YOON KWANG SUB
학회명
한국반도체학술대회