NAND and NOR Logic Gate Applications on a Single MoS2-FET with Longitudinally and Latitudinally Folded Split-Gate electrodes

초록

Two-dimensional van der Waals (2D vdWs) materials, such as molybdenum disulphide (MoS2), palladium diselenide (PdSe2), and hexagonal boron nitride (h-BN), have been widely studied as next-generation semiconductor materials due to their unique properties. For example, MoS2 channel-based FET logic circuits and memory device studies have been demonstrated for their high performances and utilizations for the future electronics. In order to organize conventional NAND (or NOR) logic gate, at least two transistors should be serially (or parallelly) connected. In this work, we demonstrated a simple method to fabricate NAND (or NOR) logic gate at the single n-type MoS2 FET. The MoS2 FET has longitudinal (or latitudinal) nano-gapped split gate electrodes, which can be considered as ‘AND-FET’ (or ‘OR-FET’) switching device. To achieve a pair of split gate electrodes, conventional photolithography and lift-off processes were employed with ZnO nanowires as a shadow mask for nanogap patterning. [1] Figure 1a and 1b show the 3D color surface of drain current (ID) of our AND-FET and OR-FET, respectively. Four distinct transition modes were observed; AA (VG1=VG2>0), DD (-VG1=-VG2>0), AD (VG1=-VG2>0), DA (-VG1=VG2>0) modes, where A and D are accumulation and depletion states of the active channel, respectively.